| TX_START | Set this bit to start sending data for channel0. |
| RX_EN | Set this bit to enbale receving data for channel0. |
| MEM_WR_RST | Set this bit to reset write ram address for channel0 by receiver access. |
| MEM_RD_RST | Set this bit to reset read ram address for channel0 by transmitter access. |
| APB_MEM_RST | Set this bit to reset W/R ram address for channel0 by apb fifo access |
| MEM_OWNER | This is the mark of channel0’s ram usage right.1’b1：receiver uses the ram 0：transmitter uses the ram |
| TX_CONTI_MODE | Set this bit to continue sending from the first data to the last data in channel0 again and again. |
| RX_FILTER_EN | This is the receive filter enable bit for channel0. |
| RX_FILTER_THRES | in receive mode channel0 ignore input pulse when the pulse width is smaller then this value. |
| REF_CNT_RST | This bit is used to reset divider in channel0. |
| REF_ALWAYS_ON | This bit is used to select base clock. 1’b1:clk_apb 1’b0:clk_ref |
| IDLE_OUT_LV | This bit configures the output signal’s level for channel0 in IDLE state. |
| IDLE_OUT_EN | This is the output enable control bit for channel0 in IDLE state. |